+45 33 73 00 20
sales@stemmer-imaging.dk

Visual Applets is a graphical programming and development environment for use of FPGA processors in imaging and machine vision. The strength of FPGAs is their capability of processing large volumes of data at high speed through parallelisation.
Visual Applets opens up completely new possibilities when working with FPGAs: The tool allows the programming of processors without expert knowledge of VHDL. It makes hardware-based imaging attractive not only for hardware programmers, but also for software engineers and algorithm engineers.
The tool maps programming solutions as graphical flow charts. Extensive libraries of operators are provided for formulating imaging algorithms. The implementation of the operators in hardware and also in software allows bit-precision simulation of the visual results at each point of the data flow model prior to synthesis. Additional information on format problems, bandwidth congestion or lack of processor resources help debugging of the hardware design. Automatic correction of timing, data synchronisation and image border effects are performed by Visual Applets simplifying the design process.
The synthesis tools of the FPGA manufacturer are integrated into Visual Applets and produce a hardware applet, following successful completion of a design. In parallel, an SDK example is generated, which can be integrated into its own application and can run immediately. The code lists all parameters defined in the design as dynamic operators, which can be changed by the software in parallel at runtime.
Visual Applets operators
+45 33 73 00 20
sales@stemmer-imaging.dk
+45 33 73 00 10
support@stemmer-imaging.dk
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